1: /*
2: * The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
3: *
4: * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
5: *
6: * Can be freely distributed and used under the terms of the GNU GPL.
7: */
8:
9: /*
10: * Under PCI, each device has 256 bytes of configuration address space,
11: * of which the first 64 bytes are standardized as follows:
12: */
13: #define PCI_VENDOR_ID 0x00 /* 16 bits */
14: #define PCI_DEVICE_ID 0x02 /* 16 bits */
15: #define PCI_COMMAND 0x04 /* 16 bits */
16: #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
17: #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
18: #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
19: #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
20: #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
21: #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
22: #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
23: #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
24: #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
25: #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
26: #define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interrupts */
27:
28: #define PCI_STATUS 0x06 /* 16 bits */
29: #define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */
30: #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
31: #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
32: #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
33: #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
34: #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
35: #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
36: #define PCI_STATUS_DEVSEL_FAST 0x000
37: #define PCI_STATUS_DEVSEL_MEDIUM 0x200
38: #define PCI_STATUS_DEVSEL_SLOW 0x400
39: #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
40: #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
41: #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
42: #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
43: #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
44:
45: #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
46: revision */
47: #define PCI_REVISION_ID 0x08 /* Revision ID */
48: #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
49: #define PCI_CLASS_DEVICE 0x0a /* Device class */
50:
51: #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
52: #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
53: #define PCI_HEADER_TYPE 0x0e /* 8 bits */
54: #define PCI_HEADER_TYPE_NORMAL 0
55: #define PCI_HEADER_TYPE_BRIDGE 1
56: #define PCI_HEADER_TYPE_CARDBUS 2
57:
58: #define PCI_BIST 0x0f /* 8 bits */
59: #define PCI_BIST_CODE_MASK 0x0f /* Return result */
60: #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
61: #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
62:
63: /*
64: * Base addresses specify locations in memory or I/O space.
65: * Decoded size can be determined by writing a value of
66: * 0xffffffff to the register, and reading it back. Only
67: * 1 bits are decoded.
68: */
69: #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
70: #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
71: #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
72: #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
73: #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
74: #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
75: #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
76: #define PCI_BASE_ADDRESS_SPACE_IO 0x01
77: #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
78: #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
79: #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
80: #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
81: #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
82: #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
83: #define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f)
84: #define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03)
85: /* bit 1 is reserved if address_space = 1 */
86:
87: /* Header type 0 (normal devices) */
88: #define PCI_CARDBUS_CIS 0x28
89: #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
90: #define PCI_SUBSYSTEM_ID 0x2e
91: #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
92: #define PCI_ROM_ADDRESS_ENABLE 0x01
93: #define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff)
94:
95: #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
96:
97: /* 0x35-0x3b are reserved */
98: #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
99: #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
100: #define PCI_MIN_GNT 0x3e /* 8 bits */
101: #define PCI_MAX_LAT 0x3f /* 8 bits */
102:
103: /* Header type 1 (PCI-to-PCI bridges) */
104: #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
105: #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
106: #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
107: #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
108: #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
109: #define PCI_IO_LIMIT 0x1d
110: #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
111: #define PCI_IO_RANGE_TYPE_16 0x00
112: #define PCI_IO_RANGE_TYPE_32 0x01
113: #define PCI_IO_RANGE_MASK ~0x0f
114: #define PCI_SEC_STATUS 0x1e /* Secondary status register */
115: #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
116: #define PCI_MEMORY_LIMIT 0x22
117: #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
118: #define PCI_MEMORY_RANGE_MASK ~0x0f
119: #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
120: #define PCI_PREF_MEMORY_LIMIT 0x26
121: #define PCI_PREF_RANGE_TYPE_MASK 0x0f
122: #define PCI_PREF_RANGE_TYPE_32 0x00
123: #define PCI_PREF_RANGE_TYPE_64 0x01
124: #define PCI_PREF_RANGE_MASK ~0x0f
125: #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
126: #define PCI_PREF_LIMIT_UPPER32 0x2c
127: #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
128: #define PCI_IO_LIMIT_UPPER16 0x32
129: /* 0x34 same as for htype 0 */
130: /* 0x35-0x3b is reserved */
131: #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
132: /* 0x3c-0x3d are same as for htype 0 */
133: #define PCI_BRIDGE_CONTROL 0x3e
134: #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
135: #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
136: #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
137: #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
138: #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
139: #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
140: #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
141: #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */
142: #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */
143: #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */
144: #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */
145:
146: /* Header type 2 (CardBus bridges) */
147: /* 0x14-0x15 reserved */
148: #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
149: #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
150: #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
151: #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
152: #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
153: #define PCI_CB_MEMORY_BASE_0 0x1c
154: #define PCI_CB_MEMORY_LIMIT_0 0x20
155: #define PCI_CB_MEMORY_BASE_1 0x24
156: #define PCI_CB_MEMORY_LIMIT_1 0x28
157: #define PCI_CB_IO_BASE_0 0x2c
158: #define PCI_CB_IO_BASE_0_HI 0x2e
159: #define PCI_CB_IO_LIMIT_0 0x30
160: #define PCI_CB_IO_LIMIT_0_HI 0x32
161: #define PCI_CB_IO_BASE_1 0x34
162: #define PCI_CB_IO_BASE_1_HI 0x36
163: #define PCI_CB_IO_LIMIT_1 0x38
164: #define PCI_CB_IO_LIMIT_1_HI 0x3a
165: #define PCI_CB_IO_RANGE_MASK ~0x03
166: /* 0x3c-0x3d are same as for htype 0 */
167: #define PCI_CB_BRIDGE_CONTROL 0x3e
168: #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
169: #define PCI_CB_BRIDGE_CTL_SERR 0x02
170: #define PCI_CB_BRIDGE_CTL_ISA 0x04
171: #define PCI_CB_BRIDGE_CTL_VGA 0x08
172: #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
173: #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
174: #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
175: #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
176: #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
177: #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
178: #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
179: #define PCI_CB_SUBSYSTEM_ID 0x42
180: #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
181: /* 0x48-0x7f reserved */
182:
183: /* Capability lists */
184:
185: #define PCI_CAP_LIST_ID 0 /* Capability ID */
186: #define PCI_CAP_ID_PM 0x01 /* Power Management */
187: #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
188: #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
189: #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
190: #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
191: #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
192: #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
193: #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
194: #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
195: #define PCI_CAP_ID_DBG 0x0A /* Debug port */
196: #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
197: #define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */
198: #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
199: #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */
200: #define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
201: #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
202: #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
203: #define PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
204: #define PCI_CAP_ID_AF 0x13 /* Advanced features of PCI devices integrated in PCIe root cplx */
205: #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
206: #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
207: #define PCI_CAP_SIZEOF 4
208:
209: /* Capabilities residing in the PCI Express extended configuration space */
210:
211: #define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
212: #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
213: #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
214: #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
215: #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
216: #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
217: #define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
218: #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
219: #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
220: #define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
221: #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
222: #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
223: #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */
224: #define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
225: #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
226: #define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */
227: #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
228:
229: /*** Definitions of capabilities ***/
230:
231: /* Power Management Registers */
232:
233: #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
234: #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
235: #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
236: #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
237: #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
238: #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
239: #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
240: #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
241: #define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
242: #define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
243: #define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
244: #define PCI_PM_CTRL 4 /* PM control and status register */
245: #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
246: #define PCI_PM_CTRL_NO_SOFT_RST 0x0008 /* No Soft Reset from D3hot to D0 */
247: #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
248: #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
249: #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
250: #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
251: #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
252: #define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
253: #define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
254: #define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
255: #define PCI_PM_SIZEOF 8
256:
257: /* AGP registers */
258:
259: #define PCI_AGP_VERSION 2 /* BCD version number */
260: #define PCI_AGP_RFU 3 /* Rest of capability flags */
261: #define PCI_AGP_STATUS 4 /* Status register */
262: #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
263: #define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */
264: #define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
265: #define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */
266: #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
267: #define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */
268: #define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */
269: #define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */
270: #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */
271: #define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */
272: #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */
273: #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */
274: #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */
275: #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */
276: #define PCI_AGP_COMMAND 8 /* Control register */
277: #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
278: #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
279: #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */
280: #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
281: #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
282: #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */
283: #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */
284: #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
285: #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
286: #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
287: #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
288: #define PCI_AGP_SIZEOF 12
289:
290: /* Vital Product Data */
291:
292: #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
293: #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
294: #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
295: #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
296:
297: /* Slot Identification */
298:
299: #define PCI_SID_ESR 2 /* Expansion Slot Register */
300: #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
301: #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
302: #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
303:
304: /* Message Signaled Interrupts registers */
305:
306: #define PCI_MSI_FLAGS 2 /* Various flags */
307: #define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */
308: #define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */
309: #define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */
310: #define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */
311: #define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */
312: #define PCI_MSI_RFU 3 /* Rest of capability flags */
313: #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
314: #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
315: #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
316: #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
317: #define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */
318: #define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */
319: #define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */
320: #define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices */
321:
322: /* PCI-X */
323: #define PCI_PCIX_COMMAND 2 /* Command register offset */
324: #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
325: #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
326: #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
327: #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
328: #define PCI_PCIX_COMMAND_RESERVED 0xf80
329: #define PCI_PCIX_STATUS 4 /* Status register offset */
330: #define PCI_PCIX_STATUS_FUNCTION 0x00000007
331: #define PCI_PCIX_STATUS_DEVICE 0x000000f8
332: #define PCI_PCIX_STATUS_BUS 0x0000ff00
333: #define PCI_PCIX_STATUS_64BIT 0x00010000
334: #define PCI_PCIX_STATUS_133MHZ 0x00020000
335: #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
336: #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
337: #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
338: #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
339: #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
340: #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
341: #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
342: #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
343: #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
344: #define PCI_PCIX_SIZEOF 4
345:
346: /* PCI-X Bridges */
347: #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
348: #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
349: #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
350: #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
351: #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
352: #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
353: #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
354: #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
355: #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
356: #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
357: #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
358: #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
359: #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
360: #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
361: #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
362: #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
363: #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
364: #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
365: #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
366: #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
367: #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
368: #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
369: #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
370: #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
371: #define PCI_PCIX_BRIDGE_SIZEOF 12
372:
373: /* HyperTransport (as of spec rev. 2.00) */
374: #define PCI_HT_CMD 2 /* Command Register */
375: #define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */
376: #define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */
377: #define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */
378: #define PCI_HT_CMD_TYP 0xf800 /* Capability Type */
379: #define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */
380: #define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */
381: #define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */
382: #define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */
383: #define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */
384: #define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */
385: #define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */
386: #define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */
387: #define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */
388: #define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */
389: #define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */
390:
391: /* Link Control Register */
392: #define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */
393: #define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */
394: #define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */
395: #define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */
396: #define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */
397: #define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */
398: #define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */
399: #define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */
400: #define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */
401: #define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */
402: #define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */
403: #define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */
404:
405: /* Link Configuration Register */
406: #define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */
407: #define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */
408: #define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */
409: #define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */
410: #define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */
411: #define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */
412: #define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */
413: #define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */
414: #define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */
415: #define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */
416: #define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */
417: #define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */
418: #define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */
419: #define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */
420:
421: /* Revision ID Register */
422: #define PCI_HT_RID_MIN 0x1f /* Minor Revision */
423: #define PCI_HT_RID_MAJ 0xe0 /* Major Revision */
424:
425: /* Link Frequency/Error Register */
426: #define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */
427: #define PCI_HT_LFRER_200 0x00 /* 200MHz */
428: #define PCI_HT_LFRER_300 0x01 /* 300MHz */
429: #define PCI_HT_LFRER_400 0x02 /* 400MHz */
430: #define PCI_HT_LFRER_500 0x03 /* 500MHz */
431: #define PCI_HT_LFRER_600 0x04 /* 600MHz */
432: #define PCI_HT_LFRER_800 0x05 /* 800MHz */
433: #define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */
434: #define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */
435: #define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */
436: #define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */
437: #define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */
438: #define PCI_HT_LFRER_ERR 0xf0 /* Link Error */
439: #define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */
440: #define PCI_HT_LFRER_OV 0x20 /* Overflow Error */
441: #define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */
442: #define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */
443:
444: /* Link Frequency Capability Register */
445: #define PCI_HT_LFCAP_200 0x0001 /* 200MHz */
446: #define PCI_HT_LFCAP_300 0x0002 /* 300MHz */
447: #define PCI_HT_LFCAP_400 0x0004 /* 400MHz */
448: #define PCI_HT_LFCAP_500 0x0008 /* 500MHz */
449: #define PCI_HT_LFCAP_600 0x0010 /* 600MHz */
450: #define PCI_HT_LFCAP_800 0x0020 /* 800MHz */
451: #define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */
452: #define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */
453: #define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */
454: #define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */
455: #define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */
456:
457: /* Feature Register */
458: #define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */
459: #define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */
460: #define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */
461: #define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */
462: #define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */
463: #define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */
464:
465: /* Error Handling Register */
466: #define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */
467: #define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */
468: #define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */
469: #define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */
470: #define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */
471: #define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */
472: #define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */
473: #define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */
474: #define PCI_HT_EH_CF 0x0100 /* Chain Fail */
475: #define PCI_HT_EH_RE 0x0200 /* Response Error */
476: #define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */
477: #define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */
478: #define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */
479: #define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */
480: #define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */
481: #define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable */
482:
483: /* HyperTransport: Slave or Primary Interface */
484: #define PCI_HT_PRI_CMD 2 /* Command Register */
485: #define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */
486: #define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */
487: #define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */
488: #define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */
489: #define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
490:
491: #define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */
492: #define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */
493: #define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */
494: #define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */
495: #define PCI_HT_PRI_RID 12 /* Revision ID Register */
496: #define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */
497: #define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */
498: #define PCI_HT_PRI_FTR 16 /* Feature Register */
499: #define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */
500: #define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */
501: #define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */
502: #define PCI_HT_PRI_EH 22 /* Error Handling Register */
503: #define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */
504: #define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */
505: #define PCI_HT_PRI_BN 26 /* Bus Number Register */
506: #define PCI_HT_PRI_SIZEOF 28
507:
508: /* HyperTransport: Host or Secondary Interface */
509: #define PCI_HT_SEC_CMD 2 /* Command Register */
510: #define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */
511: #define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */
512: #define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */
513: #define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */
514: #define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */
515: #define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */
516: #define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */
517: #define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
518:
519: #define PCI_HT_SEC_LCTR 4 /* Link Control Register */
520: #define PCI_HT_SEC_LCNF 6 /* Link Config Register */
521: #define PCI_HT_SEC_RID 8 /* Revision ID Register */
522: #define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */
523: #define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */
524: #define PCI_HT_SEC_FTR 12 /* Feature Register */
525: #define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */
526: #define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */
527: #define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */
528: #define PCI_HT_SEC_EH 18 /* Error Handling Register */
529: #define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */
530: #define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */
531: #define PCI_HT_SEC_SIZEOF 24
532:
533: /* HyperTransport: Switch */
534: #define PCI_HT_SW_CMD 2 /* Switch Command Register */
535: #define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */
536: #define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */
537: #define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */
538: #define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */
539: #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */
540: #define PCI_HT_SW_SWINF 8 /* Switch Info Register */
541: #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */
542: #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */
543: #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */
544: #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */
545: #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */
546: #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */
547: #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */
548: #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */
549: #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */
550: #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */
551: #define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */
552: #define PCI_HT_SW_SIZEOF 24
553:
554: /* Counter indices */
555: #define PCI_HT_SW_PC_PCR 0x0 /* Posted Command Receive */
556: #define PCI_HT_SW_PC_NPCR 0x1 /* Nonposted Command Receive */
557: #define PCI_HT_SW_PC_RCR 0x2 /* Response Command Receive */
558: #define PCI_HT_SW_PC_PDWR 0x3 /* Posted DW Receive */
559: #define PCI_HT_SW_PC_NPDWR 0x4 /* Nonposted DW Receive */
560: #define PCI_HT_SW_PC_RDWR 0x5 /* Response DW Receive */
561: #define PCI_HT_SW_PC_PCT 0x6 /* Posted Command Transmit */
562: #define PCI_HT_SW_PC_NPCT 0x7 /* Nonposted Command Transmit */
563: #define PCI_HT_SW_PC_RCT 0x8 /* Response Command Transmit */
564: #define PCI_HT_SW_PC_PDWT 0x9 /* Posted DW Transmit */
565: #define PCI_HT_SW_PC_NPDWT 0xa /* Nonposted DW Transmit */
566: #define PCI_HT_SW_PC_RDWT 0xb /* Response DW Transmit */
567:
568: /* Base/Limit Range indices */
569: #define PCI_HT_SW_BLR_BASE0_LO 0x0 /* Base 0[31:1], Enable */
570: #define PCI_HT_SW_BLR_BASE0_HI 0x1 /* Base 0 Upper */
571: #define PCI_HT_SW_BLR_LIM0_LO 0x2 /* Limit 0 Lower */
572: #define PCI_HT_SW_BLR_LIM0_HI 0x3 /* Limit 0 Upper */
573:
574: /* Secondary Base indices */
575: #define PCI_HT_SW_SB_LO 0x0 /* Secondary Base[31:1], Enable */
576: #define PCI_HT_SW_S0_HI 0x1 /* Secondary Base Upper */
577:
578: /* HyperTransport: Interrupt Discovery and Configuration */
579: #define PCI_HT_IDC_IDX 2 /* Index Register */
580: #define PCI_HT_IDC_DATA 4 /* Data Register */
581: #define PCI_HT_IDC_SIZEOF 8
582:
583: /* Register indices */
584: #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */
585: #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */
586: #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */
587: /* Low part (at index) */
588: #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */
589: #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */
590: #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */
591: #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */
592: #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */
593: #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */
594: /* High part (at index + 1) */
595: #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */
596: #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */
597: #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */
598:
599: /* HyperTransport: Revision ID */
600: #define PCI_HT_RID_RID 2 /* Revision Register */
601: #define PCI_HT_RID_SIZEOF 4
602:
603: /* HyperTransport: UnitID Clumping */
604: #define PCI_HT_UIDC_CS 4 /* Clumping Support Register */
605: #define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */
606: #define PCI_HT_UIDC_SIZEOF 12
607:
608: /* HyperTransport: Extended Configuration Space Access */
609: #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */
610: #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */
611: #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */
612: #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */
613: #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */
614: #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */
615: #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */
616: #define PCI_HT_ECSA_SIZEOF 12
617:
618: /* HyperTransport: Address Mapping */
619: #define PCI_HT_AM_CMD 2 /* Command Register */
620: #define PCI_HT_AM_CMD_NDMA 0x000f /* Number of DMA Mappings */
621: #define PCI_HT_AM_CMD_IOSIZ 0x01f0 /* I/O Size */
622: #define PCI_HT_AM_CMD_MT 0x0600 /* Map Type */
623: #define PCI_HT_AM_CMD_MT_40B 0x0000 /* 40-bit */
624: #define PCI_HT_AM_CMD_MT_64B 0x0200 /* 64-bit */
625:
626: /* Window Control Register bits */
627: #define PCI_HT_AM_SBW_CTR_COMP 0x1 /* Compat */
628: #define PCI_HT_AM_SBW_CTR_NCOH 0x2 /* NonCoherent */
629: #define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */
630: #define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */
631:
632: /* HyperTransport: 40-bit Address Mapping */
633: #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */
634: #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */
635: #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */
636: #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */
637: #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */
638: #define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */
639: #define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */
640: #define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */
641: #define PCI_HT_AM40_DMA_SBASE0 18 /* DMA Window Secondary Base 0 Register */
642: #define PCI_HT_AM40_SIZEOF 12 /* size is variable: 12 + 8 * NDMA */
643:
644: /* HyperTransport: 64-bit Address Mapping */
645: #define PCI_HT_AM64_IDX 4 /* Index Register */
646: #define PCI_HT_AM64_DATA_LO 8 /* Data Lower Register */
647: #define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */
648: #define PCI_HT_AM64_SIZEOF 16
649:
650: /* Register indices */
651: #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */
652: #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */
653: #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */
654: #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */
655: #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */
656: #define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */
657: #define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */
658: #define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */
659:
660: /* HyperTransport: MSI Mapping */
661: #define PCI_HT_MSIM_CMD 2 /* Command Register */
662: #define PCI_HT_MSIM_CMD_EN 0x0001 /* Mapping Active */
663: #define PCI_HT_MSIM_CMD_FIXD 0x0002 /* MSI Mapping Address Fixed */
664: #define PCI_HT_MSIM_ADDR_LO 4 /* MSI Mapping Address Lower Register */
665: #define PCI_HT_MSIM_ADDR_HI 8 /* MSI Mapping Address Upper Register */
666: #define PCI_HT_MSIM_SIZEOF 12
667:
668: /* HyperTransport: DirectRoute */
669: #define PCI_HT_DR_CMD 2 /* Command Register */
670: #define PCI_HT_DR_CMD_NDRS 0x000f /* Number of DirectRoute Spaces */
671: #define PCI_HT_DR_CMD_IDX 0x01f0 /* Index */
672: #define PCI_HT_DR_EN 4 /* Enable Vector Register */
673: #define PCI_HT_DR_DATA 8 /* Data Register */
674: #define PCI_HT_DR_SIZEOF 12
675:
676: /* Register indices */
677: #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */
678: #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */
679: #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */
680: #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */
681: #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */
682: #define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */
683:
684: /* HyperTransport: VCSet */
685: #define PCI_HT_VCS_SUP 4 /* VCSets Supported Register */
686: #define PCI_HT_VCS_L1EN 5 /* Link 1 VCSets Enabled Register */
687: #define PCI_HT_VCS_L0EN 6 /* Link 0 VCSets Enabled Register */
688: #define PCI_HT_VCS_SBD 8 /* Stream Bucket Depth Register */
689: #define PCI_HT_VCS_SINT 9 /* Stream Interval Register */
690: #define PCI_HT_VCS_SSUP 10 /* Number of Streaming VCs Supported Register */
691: #define PCI_HT_VCS_SSUP_0 0x00 /* Streaming VC 0 */
692: #define PCI_HT_VCS_SSUP_3 0x01 /* Streaming VCs 0-3 */
693: #define PCI_HT_VCS_SSUP_15 0x02 /* Streaming VCs 0-15 */
694: #define PCI_HT_VCS_NFCBD 12 /* Non-FC Bucket Depth Register */
695: #define PCI_HT_VCS_NFCINT 13 /* Non-FC Bucket Interval Register */
696: #define PCI_HT_VCS_SIZEOF 16
697:
698: /* HyperTransport: Retry Mode */
699: #define PCI_HT_RM_CTR0 4 /* Control 0 Register */
700: #define PCI_HT_RM_CTR_LRETEN 0x01 /* Link Retry Enable */
701: #define PCI_HT_RM_CTR_FSER 0x02 /* Force Single Error */
702: #define PCI_HT_RM_CTR_ROLNEN 0x04 /* Rollover Nonfatal Enable */
703: #define PCI_HT_RM_CTR_FSS 0x08 /* Force Single Stomp */
704: #define PCI_HT_RM_CTR_RETNEN 0x10 /* Retry Nonfatal Enable */
705: #define PCI_HT_RM_CTR_RETFEN 0x20 /* Retry Fatal Enable */
706: #define PCI_HT_RM_CTR_AA 0xc0 /* Allowed Attempts */
707: #define PCI_HT_RM_STS0 5 /* Status 0 Register */
708: #define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */
709: #define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */
710: #define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */
711: #define PCI_HT_RM_CTR1 6 /* Control 1 Register */
712: #define PCI_HT_RM_STS1 7 /* Status 1 Register */
713: #define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */
714: #define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */
715: #define PCI_HT_RM_SIZEOF 12
716:
717: /* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
718: #define PCI_VNDR_LENGTH 2 /* Length byte */
719:
720: /* PCI Express */
721: #define PCI_EXP_FLAGS 0x2 /* Capabilities register */
722: #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
723: #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
724: #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
725: #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
726: #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
727: #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
728: #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
729: #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
730: #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
731: #define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
732: #define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
733: #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
734: #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
735: #define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
736: #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
737: #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
738: #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
739: #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
740: #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
741: #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
742: #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
743: #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
744: #define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
745: #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
746: #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
747: #define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
748: #define PCI_EXP_DEVCTL 0x8 /* Device Control */
749: #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
750: #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
751: #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
752: #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
753: #define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
754: #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
755: #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
756: #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
757: #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
758: #define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
759: #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
760: #define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
761: #define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
762: #define PCI_EXP_DEVSTA 0xa /* Device Status */
763: #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
764: #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
765: #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
766: #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
767: #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
768: #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
769: #define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
770: #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
771: #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
772: #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
773: #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
774: #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
775: #define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
776: #define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
777: #define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
778: #define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
779: #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
780: #define PCI_EXP_LNKCTL 0x10 /* Link Control */
781: #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
782: #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
783: #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
784: #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
785: #define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
786: #define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
787: #define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
788: #define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
789: #define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
790: #define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
791: #define PCI_EXP_LNKSTA 0x12 /* Link Status */
792: #define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
793: #define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
794: #define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
795: #define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
796: #define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
797: #define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
798: #define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
799: #define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
800: #define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
801: #define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
802: #define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
803: #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
804: #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
805: #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
806: #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
807: #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
808: #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
809: #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
810: #define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
811: #define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
812: #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
813: #define PCI_EXP_SLTCTL 0x18 /* Slot Control */
814: #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
815: #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
816: #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
817: #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
818: #define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
819: #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
820: #define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
821: #define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
822: #define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
823: #define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
824: #define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
825: #define PCI_EXP_SLTSTA 0x1a /* Slot Status */
826: #define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
827: #define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
828: #define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
829: #define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
830: #define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
831: #define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
832: #define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
833: #define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
834: #define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
835: #define PCI_EXP_RTCTL 0x1c /* Root Control */
836: #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
837: #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
838: #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
839: #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
840: #define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
841: #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
842: #define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
843: #define PCI_EXP_RTSTA 0x20 /* Root Status */
844: #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
845: #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
846: #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
847: #define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
848: #define PCI_EXP_DEVCTL2 0x28 /* Device Control */
849: #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
850: #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
851: #define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
852: #define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
853: #define PCI_EXP_DEVSTA2 0x2a /* Device Status */
854: #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
855: #define PCI_EXP_LNKCTL2 0x30 /* Link Control */
856: #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
857: #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */
858: #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */
859: #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */
860: #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */
861: #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */
862: #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */
863: #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance De-emphasis */
864: #define PCI_EXP_LNKSTA2 0x32 /* Link Status */
865: #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */
866: #define PCI_EXP_LINKSTA2_EQU_COMP 0x02 /* Equalization Complete */
867: #define PCI_EXP_LINKSTA2_EQU_PHASE1 0x04 /* Equalization Phase 1 Successful */
868: #define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Successful */
869: #define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Successful */
870: #define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request */
871: #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
872: #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
873: #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
874:
875: /* MSI-X */
876: #define PCI_MSIX_ENABLE 0x8000
877: #define PCI_MSIX_MASK 0x4000
878: #define PCI_MSIX_TABSIZE 0x07ff
879: #define PCI_MSIX_TABLE 4
880: #define PCI_MSIX_PBA 8
881: #define PCI_MSIX_BIR 0x7
882:
883: /* Subsystem vendor/device ID for PCI bridges */
884: #define PCI_SSVID_VENDOR 4
885: #define PCI_SSVID_DEVICE 6
886:
887: /* PCI Advanced Features */
888: #define PCI_AF_CAP 3
889: #define PCI_AF_CAP_TP 0x01
890: #define PCI_AF_CAP_FLR 0x02
891: #define PCI_AF_CTRL 4
892: #define PCI_AF_CTRL_FLR 0x01
893: #define PCI_AF_STATUS 5
894: #define PCI_AF_STATUS_TP 0x01
895:
896: /* SATA Host Bus Adapter */
897: #define PCI_SATA_HBA_BARS 4
898: #define PCI_SATA_HBA_REG0 8
899:
900: /*** Definitions of extended capabilities ***/
901:
902: /* Advanced Error Reporting */
903: #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
904: #define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
905: #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
906: #define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
907: #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
908: #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
909: #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
910: #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
911: #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
912: #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
913: #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
914: #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
915: #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
916: #define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */
917: #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
918: /* Same bits as above */
919: #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
920: /* Same bits as above */
921: #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
922: #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
923: #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
924: #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
925: #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
926: #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
927: #define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */
928: #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
929: /* Same bits as above */
930: #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
931: #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
932: #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
933: #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
934: #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
935: #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
936: #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
937: #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
938: #define PCI_ERR_ROOT_STATUS 48
939: #define PCI_ERR_ROOT_COR_SRC 52
940: #define PCI_ERR_ROOT_SRC 54
941:
942: /* Virtual Channel */
943: #define PCI_VC_PORT_REG1 4
944: #define PCI_VC_PORT_REG2 8
945: #define PCI_VC_PORT_CTRL 12
946: #define PCI_VC_PORT_STATUS 14
947: #define PCI_VC_RES_CAP 16
948: #define PCI_VC_RES_CTRL 20
949: #define PCI_VC_RES_STATUS 26
950:
951: /* Power Budgeting */
952: #define PCI_PWR_DSR 4 /* Data Select Register */
953: #define PCI_PWR_DATA 8 /* Data Register */
954: #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
955: #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
956: #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
957: #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
958: #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
959: #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
960: #define PCI_PWR_CAP 12 /* Capability */
961: #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
962:
963: /* Root Complex Link */
964: #define PCI_RCLINK_ESD 4 /* Element Self Description */
965: #define PCI_RCLINK_LINK1 16 /* First Link Entry */
966: #define PCI_RCLINK_LINK_DESC 0 /* Link Entry: Description */
967: #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
968: #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
969:
970: /* PCIe Vendor-Specific Capability */
971: #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
972: #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
973:
974: /* Access Control Services */
975: #define PCI_ACS_CAP 0x04 /* ACS Capability Register */
976: #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
977: #define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
978: #define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
979: #define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
980: #define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
981: #define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
982: #define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
983: #define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */
984: #define PCI_ACS_CTRL 0x06 /* ACS Control Register */
985: #define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */
986: #define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */
987: #define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */
988: #define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */
989: #define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */
990: #define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */
991: #define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */
992: #define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */
993:
994: /* Alternative Routing-ID Interpretation */
995: #define PCI_ARI_CAP 0x04 /* ARI Capability Register */
996: #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
997: #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
998: #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
999: #define PCI_ARI_CTRL 0x06 /* ARI Control Register */
1000: #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
1001: #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
1002: #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
1003:
1004: /* Address Translation Service */
1005: #define PCI_ATS_CAP 0x04 /* ATS Capability Register */
1006: #define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */
1007: #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
1008: #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
1009: #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
1010:
1011: /* Single Root I/O Virtualization */
1012: #define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
1013: #define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
1014: #define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
1015: #define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
1016: #define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
1017: #define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
1018: #define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
1019: #define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
1020: #define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
1021: #define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
1022: #define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
1023: #define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
1024: #define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */
1025: #define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */
1026: #define PCI_IOV_FDL 0x12 /* Function Dependency Link */
1027: #define PCI_IOV_OFFSET 0x14 /* First VF Offset */
1028: #define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */
1029: #define PCI_IOV_DID 0x1a /* VF Device ID */
1030: #define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
1031: #define PCI_IOV_SYSPS 0x20 /* System Page Size */
1032: #define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
1033: #define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
1034: #define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */
1035: #define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
1036: #define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */
1037:
1038: /* Transaction Processing Hints */
1039: #define PCI_TPH_CAPABILITIES 4
1040: #define PCI_TPH_INTVEC_SUP (1<<1) /* Supports interrupt vector mode */
1041: #define PCI_TPH_DEV_SUP (1<<2) /* Device specific mode supported */
1042: #define PCI_TPH_EXT_REQ_SUP (1<<8) /* Supports extended requests */
1043: #define PCI_TPH_ST_LOC_MASK (3<<9) /* Steering table location bits */
1044: #define PCI_TPH_ST_NONE (0<<9) /* No steering table */
1045: #define PCI_TPH_ST_CAP (1<<9) /* Steering table in TPH cap */
1046: #define PCI_TPH_ST_MSIX (2<<9) /* Steering table in MSI-X table */
1047: #define PCI_TPH_ST_SIZE_SHIFT (16) /* Encoded as size - 1 */
1048:
1049: /* Latency Tolerance Reporting */
1050: #define PCI_LTR_MAX_SNOOP 4 /* 16 bit value */
1051: #define PCI_LTR_VALUE_MASK (0x3ff)
1052: #define PCI_LTR_SCALE_SHIFT (10)
1053: #define PCI_LTR_SCALE_MASK (7)
1054: #define PCI_LTR_MAX_NOSNOOP 6 /* 16 bit value */
1055:
1056: /*
1057: * The PCI interface treats multi-function devices as independent
1058: * devices. The slot/function address of each device is encoded
1059: * in a single byte as follows:
1060: *
1061: * 7:3 = slot
1062: * 2:0 = function
1063: */
1064: #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1065: #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
1066: #define PCI_FUNC(devfn) ((devfn) & 0x07)
1067:
1068: /* Device classes and subclasses */
1069:
1070: #define PCI_CLASS_NOT_DEFINED 0x0000
1071: #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
1072:
1073: #define PCI_BASE_CLASS_STORAGE 0x01
1074: #define PCI_CLASS_STORAGE_SCSI 0x0100
1075: #define PCI_CLASS_STORAGE_IDE 0x0101
1076: #define PCI_CLASS_STORAGE_FLOPPY 0x0102
1077: #define PCI_CLASS_STORAGE_IPI 0x0103
1078: #define PCI_CLASS_STORAGE_RAID 0x0104
1079: #define PCI_CLASS_STORAGE_ATA 0x0105
1080: #define PCI_CLASS_STORAGE_SATA 0x0106
1081: #define PCI_CLASS_STORAGE_SAS 0x0107
1082: #define PCI_CLASS_STORAGE_OTHER 0x0180
1083:
1084: #define PCI_BASE_CLASS_NETWORK 0x02
1085: #define PCI_CLASS_NETWORK_ETHERNET 0x0200
1086: #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
1087: #define PCI_CLASS_NETWORK_FDDI 0x0202
1088: #define PCI_CLASS_NETWORK_ATM 0x0203
1089: #define PCI_CLASS_NETWORK_ISDN 0x0204
1090: #define PCI_CLASS_NETWORK_OTHER 0x0280
1091:
1092: #define PCI_BASE_CLASS_DISPLAY 0x03
1093: #define PCI_CLASS_DISPLAY_VGA 0x0300
1094: #define PCI_CLASS_DISPLAY_XGA 0x0301
1095: #define PCI_CLASS_DISPLAY_3D 0x0302
1096: #define PCI_CLASS_DISPLAY_OTHER 0x0380
1097:
1098: #define PCI_BASE_CLASS_MULTIMEDIA 0x04
1099: #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
1100: #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
1101: #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
1102: #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV 0x0403
1103: #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
1104:
1105: #define PCI_BASE_CLASS_MEMORY 0x05
1106: #define PCI_CLASS_MEMORY_RAM 0x0500
1107: #define PCI_CLASS_MEMORY_FLASH 0x0501
1108: #define PCI_CLASS_MEMORY_OTHER 0x0580
1109:
1110: #define PCI_BASE_CLASS_BRIDGE 0x06
1111: #define PCI_CLASS_BRIDGE_HOST 0x0600
1112: #define PCI_CLASS_BRIDGE_ISA 0x0601
1113: #define PCI_CLASS_BRIDGE_EISA 0x0602
1114: #define PCI_CLASS_BRIDGE_MC 0x0603
1115: #define PCI_CLASS_BRIDGE_PCI 0x0604
1116: #define PCI_CLASS_BRIDGE_PCMCIA 0x0605
1117: #define PCI_CLASS_BRIDGE_NUBUS 0x0606
1118: #define PCI_CLASS_BRIDGE_CARDBUS 0x0607
1119: #define PCI_CLASS_BRIDGE_RACEWAY 0x0608
1120: #define PCI_CLASS_BRIDGE_PCI_SEMI 0x0609
1121: #define PCI_CLASS_BRIDGE_IB_TO_PCI 0x060a
1122: #define PCI_CLASS_BRIDGE_OTHER 0x0680
1123:
1124: #define PCI_BASE_CLASS_COMMUNICATION 0x07
1125: #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
1126: #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
1127: #define PCI_CLASS_COMMUNICATION_MSERIAL 0x0702
1128: #define PCI_CLASS_COMMUNICATION_MODEM 0x0703
1129: #define PCI_CLASS_COMMUNICATION_OTHER 0x0780
1130:
1131: #define PCI_BASE_CLASS_SYSTEM 0x08
1132: #define PCI_CLASS_SYSTEM_PIC 0x0800
1133: #define PCI_CLASS_SYSTEM_DMA 0x0801
1134: #define PCI_CLASS_SYSTEM_TIMER 0x0802
1135: #define PCI_CLASS_SYSTEM_RTC 0x0803
1136: #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
1137: #define PCI_CLASS_SYSTEM_OTHER 0x0880
1138:
1139: #define PCI_BASE_CLASS_INPUT 0x09
1140: #define PCI_CLASS_INPUT_KEYBOARD 0x0900
1141: #define PCI_CLASS_INPUT_PEN 0x0901
1142: #define PCI_CLASS_INPUT_MOUSE 0x0902
1143: #define PCI_CLASS_INPUT_SCANNER 0x0903
1144: #define PCI_CLASS_INPUT_GAMEPORT 0x0904
1145: #define PCI_CLASS_INPUT_OTHER 0x0980
1146:
1147: #define PCI_BASE_CLASS_DOCKING 0x0a
1148: #define PCI_CLASS_DOCKING_GENERIC 0x0a00
1149: #define PCI_CLASS_DOCKING_OTHER 0x0a80
1150:
1151: #define PCI_BASE_CLASS_PROCESSOR 0x0b
1152: #define PCI_CLASS_PROCESSOR_386 0x0b00
1153: #define PCI_CLASS_PROCESSOR_486 0x0b01
1154: #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
1155: #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
1156: #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
1157: #define PCI_CLASS_PROCESSOR_MIPS 0x0b30
1158: #define PCI_CLASS_PROCESSOR_CO 0x0b40
1159:
1160: #define PCI_BASE_CLASS_SERIAL 0x0c
1161: #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
1162: #define PCI_CLASS_SERIAL_ACCESS 0x0c01
1163: #define PCI_CLASS_SERIAL_SSA 0x0c02
1164: #define PCI_CLASS_SERIAL_USB 0x0c03
1165: #define PCI_CLASS_SERIAL_FIBER 0x0c04
1166: #define PCI_CLASS_SERIAL_SMBUS 0x0c05
1167: #define PCI_CLASS_SERIAL_INFINIBAND 0x0c06
1168:
1169: #define PCI_BASE_CLASS_WIRELESS 0x0d
1170: #define PCI_CLASS_WIRELESS_IRDA 0x0d00
1171: #define PCI_CLASS_WIRELESS_CONSUMER_IR 0x0d01
1172: #define PCI_CLASS_WIRELESS_RF 0x0d10
1173: #define PCI_CLASS_WIRELESS_OTHER 0x0d80
1174:
1175: #define PCI_BASE_CLASS_INTELLIGENT 0x0e
1176: #define PCI_CLASS_INTELLIGENT_I2O 0x0e00
1177:
1178: #define PCI_BASE_CLASS_SATELLITE 0x0f
1179: #define PCI_CLASS_SATELLITE_TV 0x0f00
1180: #define PCI_CLASS_SATELLITE_AUDIO 0x0f01
1181: #define PCI_CLASS_SATELLITE_VOICE 0x0f03
1182: #define PCI_CLASS_SATELLITE_DATA 0x0f04
1183:
1184: #define PCI_BASE_CLASS_CRYPT 0x10
1185: #define PCI_CLASS_CRYPT_NETWORK 0x1000
1186: #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1010
1187: #define PCI_CLASS_CRYPT_OTHER 0x1080
1188:
1189: #define PCI_BASE_CLASS_SIGNAL 0x11
1190: #define PCI_CLASS_SIGNAL_DPIO 0x1100
1191: #define PCI_CLASS_SIGNAL_PERF_CTR 0x1101
1192: #define PCI_CLASS_SIGNAL_SYNCHRONIZER 0x1110
1193: #define PCI_CLASS_SIGNAL_OTHER 0x1180
1194:
1195: #define PCI_CLASS_OTHERS 0xff
1196:
1197: /* Several ID's we need in the library */
1198:
1199: #define PCI_VENDOR_ID_INTEL 0x8086
1200: #define PCI_VENDOR_ID_COMPAQ 0x0e11
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